Chip on Glass (COG) technology is widely used to mount driver ICs on Liquid Crystal Display (LCD) substrates. We have developed Resin Core Bump technology as a novel COG technology. Unlike conventional COG bonding with Anisotropic Conductive Film (ACF), Resin Core Bump structures form stable interconnections by direct contact between the bump and the substrate. Moreover, the bump and its bonding structures are optimized to achieve a fine-pitch interconnection. In this paper, we report the results of our evaluation of the fine pitch bondability and interconnection reliability of Resin Core Bumps using 20 μm-pitch test samples. Reliability was evaluated by a Thermal Cycle Test and Thermal Humidity Bias Test. The initial contact resistance was even more stable than with a 40 μm conventional COG structure. The maximum resistance increment was less than 2.0 Ω after 2000 cycles.

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The primary motive for optical interconnection is the realization of high-throughput data transmission beyond the speed of electrical transmission in high-end systems. The data throughput of a back plane in routers and servers is also well over Tbps. This paper describes a miniature optical transceiver named Photonic/Electronic Tied InTerface (PETIT) for on-board optical interconnection. 40 Gbps (10 Gbps by 4 ch) throughput with a size of 14 mm square is realized. PETITs are placed on or near the LSI package to minimize the length of the electrical signal lines to eliminate increased power consumption. An approach for the optical wiring system is also introduced after a description of the PETIT design and a demonstration of 10 Gbps operation.

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The dynamic power noise of digital large scale integration (LSI) has a major impact on LSI performance as well as on the electromagnetic performance of electronic systems. Accurate understanding of power noise generation, noise propagation, and their interaction with circuit operation are necessary in order to ensure correct design considerations. This article discusses power noise problems in LSIs and introduces on-chip noise monitoring and chip-level noise simulation technologies.

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Complicated local distribution of residual stress and strain occurs in flip-chip structures due to the difference in material properties such as the coefficients of thermal expansion and elastic modulus among metallic bumps, underfill material, the silicon chip and the substrate. The residual stress was measured using newly-developed strain sensor chips with 2-μm long piezoresistance gauges. As a result of three dimensional analyses and the experiment, it was found that the amplitude of the residual stress in the stacked chips reached about 300 MPa. In addition, both isotropic and anisotropic normal stress fields appeared locally on the chip surface depending on the bump alignment. The magnitude of the difference in the anisotropic residual normal stress reached 150 MPa.

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In this paper, we present a method of miniaturization for a wideband filter in a low-temperature co-fired ceramic (LTCC) substrate. The presented method uses a spiral strip line consisting of multilayer structures, which realizes a very small shape compared to normal meandering structures or spiral structures. The presented structure is applied to wideband filters with the aid of Smith charts. We also verify the presented method by prototyping very small wideband filters in the LTCC substrate.

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In this paper, we suggest a practical simulation method for estimating the fatigue life of a solder joint on a chip component, which is the most severe component of lead-free solder-joint reliability in automotive electronic components. The complicated behavior of crack propagation in the solder joint was revealed using the proposed method. The shape of the solder joints affects the crack propagation mode of the joint. In particular, the crack of the solder joint propagated along the side of the chip component or through the solder fillet. In the case of the crack through the solder fillet, the fatigue life of the solder joint decreases significantly. Also, a high reliability design method for solder joints on chip components was indicated using the relation between the shapes of the solder joints and the crack propagation modes. Furthermore, the availability and applicability of this method for other chip components was validated by experiment.

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This paper presents a reflow process simulation for estimating lead-free solder joint shapes on the chip component that was the most severe reliability test of solder joints in automotive electronic components. The simulation was in good agreement with experimental results. The effect of the reflow process variation on the solder joint shape was evaluated using a reflow process simulation, and the interaction of the reflow process factors was verified. It was shown that the effect of the Reflow process variation on solder joint reliability could be evaluated using a fatigue life analysis of the estimated solder joint shapes in consideration of the reflow process variation.

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